1. Field of the Invention
Embodiments of the present invention generally relate to leakage currents in integrated circuit (IC) devices.
2. Description of the Related Art
Modern mobile electronic devices such as digital music players, portable digital assistants (PDAs), cell phones, and laptops require increasing amounts of memory to handle the computing demands of users of the devices. Accordingly, modern mobile electronic devices typically employ some sort of random access memory (RAM), such as dynamic random access memory (DRAM), either as a separate integrated circuit (IC) or combined with a processor, for instance as part of a cache or a system on a chip (SOC). DRAM memories consume power, and because mobile electronic devices may have a limited power supply provided by a battery, there is an increased demand for low-power memories for use in such mobile devices. Such low-power memories may include low-power single data rate (LP-SDR) DRAM, low-power double data rate (LP-DDR) DRAM, and pseudo-static RAM (PSRAM).
FIG. 1 is a block diagram depicting an exemplary memory device 100. The memory device may have control circuits 102 accessed using a memory I/O interface. The control circuits 102 may be used to access one or memory arrays 104 of the memory and may issue control signals to components within the memory array 104. FIG. 2 is a block diagram depicting an exemplary memory array 104. The memory array 104 may contain a row decoder 210 and a column decoder 220. Each time a memory address in the memory array 104 is accessed, the address may be decoded by the row decoder 210 and column decoder 220 to determine at which row (also referred to as a wordline or main wordline 240) and which column (also referred to as a bitline 250) in the array the memory address resides. When the memory address is decoded by the row decoder 210 to select a wordline 240 from the memory array 104, a main wordline driver 212 may drive a signal (MWL) onto the selected wordline 240, thus enabling data to be accessed from the selected wordline 240. The memory array 104 may also contain many other elements (not shown), such as sense amplifiers, which may be used to access (e.g., read, write, or refresh) the memory array 104.
In some cases, the memory device 100 may utilize a segmented wordline structure. In a segmented wordline structure, each memory array 104 may contain multiple memory segments 230 and each segment may contain an array of memory cells 218. To activate the memory cells 218 in each memory segment 230, the row decoder 210 may first be used to decode the memory address and select a segment 230 within the memory array 104. After a segment 230 has been selected, the memory address may be further decoded to access a local row (referred to as a local wordline 242) within the segment 230. The process of decoding a memory address to select a segment 230 and a local wordline 242 within a segment may be referred to as hierarchical decoding.
Each local wordline 242 may have a local wordline driver 216 used to drive the local wordline 242. For any one memory address being accessed, one wordline 240 and one local wordline 242 may be activated while many wordlines 240 and many local wordlines 242 are not activated. The wordline 240 and the local wordline which are selected may be in what is referred to as an operational mode. The wordlines 240 and local wordlines 242 which are not selected may, in some cases, be in a state or mode referred to as a standby state or standby mode.
A signal (referred to as WLON) output by a wordline decoder 214 to each local wordline driver 216 may be used to determine whether the local wordline driver 216 is activated. Each wordline decoder 214 may control several local wordline drivers 216 (also referred to as a column or cluster of local wordline drivers 216). When WLON is asserted to a high voltage and MWL is also a high voltage, the local wordline driver 216 may be activated. When WLON is lowered to a low voltage (e.g., VSS), the local wordline driver 216 may be inactive. When a wordline 242 is inactive, it may be reset using a wordline reset signal (WLRST).
FIG. 3 is a circuit diagram depicting an exemplary local wordline driver 216. The local wordline driver may have an inverter (PMOS transistor P1 302 and NMOS transistor N1 304) which drives local wordline 242 as well as a reset transistor (NMOS transistor N2 306) which resets local wordline 242. The inverter may be controlled by the bMWL signal (the complement of the MWL signal) and the reset transistor 306 may be driven by bWLRST signal (the complement of the WLRST signal).
Operation of the Local Wordline Driver
Table 1 depicts the signals used to control the local wordline driver 216 as well as the corresponding state of the local wordline driver 216.
TABLE 1Local Wordline Driver StatesWordlineDriverDriver StatebMWLWLONbWLRSTOutputWordline selected,VWLOFFVSSVDDVWLOFFlocal wordline drivernot selectedWordline and localVWLOFFVPPVWLOFFVPPwordline selectedMain wordline notVPPVPPVWLOFFVWLOFFselected, local wordlinedriver selectedStandby modeVPPVSSVDDVWLOFF
If a memory access is made which utilizes a given main wordline 240 and local wordline 242, the wordline driver 212 for the main wordline 240 may assert the MWL signal, selecting the main wordline 240. When the MWL signal for the main wordline 240 is asserted, the bMWL signal may be lowered, driving the WLON value for the local wordline driver 216 through the PMOS transistor P1 302. If bMWL is lowered and the local wordline 242 is not selected during a memory access, a low power supply voltage (VSS) may be applied to WLON and driven onto the local wordline 242. If bMWL is lowered and the local wordline 242 is selected during a memory access, the wordline decoder 214 for the local wordline driver 216 asserts the WLON signal to a boosted high voltage (VPP), and the asserted WLON signal is driven onto the local wordline 242, allowing the local wordline 242 to be accessed. In some cases, the main wordline 240 for a local wordline driver 216 may not be selected (bMWL=VPP), but the column of local wordline drivers controlled by a wordline decoder 214 containing the local wordline driver 216 may be selected (WLON=VPP). In such a case, the local wordline 242 is not selected, and the output of the local wordline driver 216 is VWLOFF.
The boosted high voltage VPP (also referred to as the upward-driven high voltage) may be maintained by a charge pump. A charge pump is a circuit which may utilize a capacitor to increase a voltage above a positive power supply voltage or decrease a voltage below a negative power supply voltage. Thus, VPP may be greater than a positive power supply voltage (referred to as VDD) utilized by the memory device 100.
The local wordline 242 is typically driven to the boosted high voltage VPP (also referred to as VCCP, or VCC pumped, where VCC is the high power supply voltage) so that the high power supply voltage VCC (also referred to as VDD) can be successfully written into memory cells in the memory array 104, for example, by compensating for switching transistor voltage drops. In some cases, the switching transistor voltage drops may be due partly to a threshold voltage of the switching transistor (referred to as VTH) and the boosted voltage may be selected to overcome the threshold voltage when a high voltage is being written to the memory cell, such that VPP is equal to VCC+VTH.
When an access to the main wordline 240 is not occurring, the main wordline 240 and local wordline 242 may be deselected. Thus, for the main wordline 240, the MWL signal may be lowered to a low value, and bMWL may be raised to a high logic value, VPP. For the local wordline 242, the local wordline signal WLON may be lowered to VSS (deselecting the local wordline 242) and the wordline reset signal WLRST may be asserted, lowering bWLRST to a low logic value and causing the local wordline 242 to be reset to a wordline off voltage. In some cases, the wordline off voltage may be a low voltage, VSS. In other cases, the wordline off voltage may the downward-driven low voltage VWLOFF (also referred to as a downward-boosted low voltage) which may be maintained by a charge pump. Thus, VWLOFF may be a lower voltage (e.g., a negative voltage) than the low power supply voltage VSS. When the main wordline 240 and the local wordline 242 are not selected, the local wordline driver 216 may be in the standby mode.
FIG. 4 is a substrate view depicting an exemplary PMOS transistor P1 302 in a local wordline driver 216 during a standby mode. The PMOS transistor 302 may have a gate 402, a gate oxide layer 410, a source 406, a drain 404, and may be located in an N-well 408 (sometimes referred to as the substrate with respect to a PMOS transistor). When the local wordline driver 216 is in standby mode, the gate voltage may be VPP, the source voltage may be VSS, and the drain voltage may be VWLOFF. The N-well substrate voltage may also be VPP. Applying a voltage to the N-well 408 may be referred to as biasing. Biasing the N-well substrate 408 may lower the threshold voltage (VTH) of the PMOS transistor P1 302 and improve the operating characteristics of the PMOS transistor 302.
When the transistor is in the standby mode, the gate to drain voltage (VGD) may be large (VPP+|VWLOFF|) because both the gate and drain voltages (VPP and VWLOFF, respectively) are being driven by charge pumps. This creates a strong reverse bias across the gate 402 and drain 404. When there is a strong reverse bias across the gate 402 and drain 404, an effect known as Gate-Induced Drain Leakage (GIDL) may develop. GIDL creates a current (labeled IGIDL) flowing from the N-well substrate 408 to the drain 404 (in some cases, the direction is from the drain 404 to the N-well substrate 408). IGIDL is proportional to the voltage difference between the gate 402 and drain 404, and may be caused by band to band tunneling (BTBT) and/or trap assisted tunneling (TAT) of electrons occurring in the drain region 404. The negatively-charged electrons flow from the drain 404 to the N-well substrate 408, creating IGIDL. Conventionally, the direction of current flow is defined as the flow of positive charge, so the direction of IGIDL is from the N-well 408 to the drain 404 (opposite the direction of the flow of electrons). Because the IGIDL flows from the N-well 408 to the drain 404, the current due to GIDL may also be increased by the N-well bias (VPP) and the drain bias VWLOFF which may both be driven by charge pumps (VPP is driven upwards, VWLOFF is driven downwards).
Thus, even though the local wordline driver 216 is in a standby mode, a significant leakage current due to GIDL may drain power from the driver 216. The power consumption may be increased by the charge pumps which drive VWLOFF and VPP. The increased power consumption may be due to both the increased bias across the gate 402 and drain 404 and may also be due to inefficiency of the charge pumps which consume power while maintaining VWLOFF and VPP. The GIDL effect may also be increased by aspects of the process used to manufacture the memory device 100, such as decreased gate oxide thickness or doping in transistors of the memory device 100.
Referring back to FIG. 2, as depicted, each segment 230 in a memory array 104 may have several local wordline drivers 216, and due to the large number of segments 230, the memory array 104 may contain a large number of local wordline drivers 216, each of which may be placed in a standby mode. Because of the large number of local wordline drivers 216 in standby mode, the total leakage current and power loss due to GIDL may become substantial. A specification for a DRAM device may require low power consumption. The leakage current due to GIDL may cause the DRAM device to fail to meet the desired specification.
Accordingly, what is needed is a wordline driver for and method of suppressing a leakage current.